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asix electronics corporation frist released date : oct/02/1998 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw AX88190P pcmcia fast ethernet mac controller 10/100base pcmcia fast ethernet mac controller document no.: ax190-16 / v1.6 / may. 12 ? 00 features ieee 802.3u 100base-t, tx, and t4 compatible single chip pc mc i a bus 10/100mbps fast ethernet mac controller ne2000 register level compatible instruction compliant with 16 bit pc card standard - february 1995 support both 10mbps and 100mbps data rate support both full-duplex or half-duplex operation provides a mii port for both 10/100mbps operation support 256/512 bytes eeprom (used for saving cis) support automatic loading of ethernet id, cis and adapter configuration from eeprom on power- on initialization external and internal loop-back capability 128-pin lqfp low profile package 2 5mhz operation, dual 5v and 3.3 v cmos process with 5v i/o tolerance . or pure 3.3v operation *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88190 fast ethernet controller is a high performance pc mc i a bus ethernet controller. the ax88190 contains a 16 bit pc mc i a interf ace s to host cpu and compliant with pc card standard ? february 1995 . the ax88190 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the ax88190 supports 10mbps/100mbps media-independent interface (mii) to simplify the design. the ax88190 is built in interface to connect fax/modem chipset with parallel bus interface. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electronics reserves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. ax88190 phy/txrx modem daa magnetic rj45 rj11 pcmcia i/f eeprom sram
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 2 contents 1.0 introduction ................................ ................................ ................................ ................................ ............... 5 1.1 g eneral d escription : ................................ ................................ ................................ ................................ ..... 5 1.2 ax88190 b lock d iagram : ................................ ................................ ................................ ............................... 5 1.3 ax88190 p in c onnection d iagram ................................ ................................ ................................ ................ 6 2.0 signal description ................................ ................................ ................................ ................................ .... 7 2.1 pcmcia b us i nterface s ignals g roup ................................ ................................ ................................ ......... 7 2.2 eeprom s ignals g roup ................................ ................................ ................................ ................................ . 8 2.3 mii interface signals group ................................ ................................ ................................ .......................... 8 2.4 m odem interface pins group ................................ ................................ ................................ .......................... 9 2.5 sram i nterface pins group ................................ ................................ ................................ ........................... 9 2.6 m iscellaneous pins group ................................ ................................ ................................ ............................ 10 2.7 p ower on configuration setup signals cross reference table ................................ ................................ . 10 3.0 memory and i/o mapping ................................ ................................ ................................ ..................... 11 3.1 eeprom m emory m apping ................................ ................................ ................................ .......................... 11 3.2 a ttribute m emory m apping ................................ ................................ ................................ ......................... 11 3.3 i/o m apping ................................ ................................ ................................ ................................ .................... 12 3.4 sram m emory m apping ................................ ................................ ................................ ............................... 12 4.0 registers operation ................................ ................................ ................................ .............................. 13 4.1 pcmcia f unction c onfiguration r egister s et of lan ................................ ................................ ............ 13 4.1.1 configuration option register of lan (lcor) offset 3c0h (read/write) ................................ ............... 14 4.1.2 configuration and status register of lan (lcsr) offset 3c2h (read/write) ................................ .......... 15 4.1.3 i/o base register 0/1 of lan (liobase0/1) offset 3cah/3cch (read/write) ................................ ....... 15 4.2 pcmcia f unction c onfiguration r egister s et of modem ................................ ................................ ..... 16 4.2.1 configuration option register of modem (mcor) offset 3e0h (read/write) ................................ ....... 16 4.2.2 configuration and status register of modem (mcsr) offset 3e2h (read/write) ................................ .. 17 4.2.3 i/o base register 0/1 of modem (miobase0/1) offset 3eah/3ech (read/write) ............................... 17 4.3 r egisters o peration ................................ ................................ ................................ ................................ ..... 18 4.3.1 command register (cr) offset 00h (read/write) ................................ ................................ .................... 20 4.3.2 interrupt status register (isr) offset 07h (read/write) ................................ ................................ ........... 20 4.3.3 interrupt mask register (imr) offset 0fh (write) ................................ ................................ .................... 21 4.3.4 data configuration register (dcr) offset 0eh (write) ................................ ................................ ........... 21 4.3.5 transmit configuration register (tcr) offset 0dh (write) ................................ ................................ ..... 21 4.3.6 transmit status register (tsr) offset 04h (read) ................................ ................................ ................... 22 4.3.7 receive configuration (rcr) offset 0ch (write) ................................ ................................ .................... 22 4.3.8 receive status register (rsr) offset 0ch (read) ................................ ................................ .................... 22 4.3.9 inter-frame gap (ifg) offset 16h (read/write) ................................ ................................ ........................ 22 4.3.10 inter-frame gap segment 1(ifgs1) offset 12h (read/write) ................................ ................................ .. 23 4.3.11 inter-frame gap segment 2(ifgs2) offset 13h (read/write) ................................ ................................ .. 23 4.3.12 mii/eeprom management register (memr) offset 14h (read/write) ................................ ................. 23 4.3.13 test register (tr) offset 15h (write) ................................ ................................ ................................ ..... 23 5.0 pcmcia device access functions ................................ ................................ ................................ .... 24 5.1 a ttribute m emory access function functions . ................................ ................................ ......................... 24 5.2 i/o access function functions . ................................ ................................ ................................ .................... 24 6.0 electrical specification and timings ................................ ................................ ....................... 25 6.1 a bsolute m aximum r atings ................................ ................................ ................................ ......................... 25 6.2 g eneral o peration c onditions ................................ ................................ ................................ ................... 25 6.3 dc c haracteristics ................................ ................................ ................................ ................................ ...... 25
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 3 6.4 a.c. t iming c haracteristics ................................ ................................ ................................ ........................ 26 6.4.1 xtal / clock ................................ ................................ ................................ ................................ ......... 26 6.4.2 reset timing ................................ ................................ ................................ ................................ ............. 26 6.4.3 attribute memory read timing ................................ ................................ ................................ ................. 27 6.4.4 attribute memory write timing ................................ ................................ ................................ ................ 28 6.4.5 i/o read timing ................................ ................................ ................................ ................................ ....... 29 6.4.6 i/o write timing ................................ ................................ ................................ ................................ ....... 30 6.4.7 mii timing ................................ ................................ ................................ ................................ ................ 31 6.4.8 asynchronous memory i/f access timing ................................ ................................ ................................ . 32 7.0 package information ................................ ................................ ................................ ........................... 33 appendix a: application note 1 ................................ ................................ ................................ .............. 34 a.1 u sing c rystal ................................ ................................ ................................ ................................ .............. 34 a.2 u sing o scillator ................................ ................................ ................................ ................................ ......... 34 a.3 d ual power (5v and 3.3v) application ................................ ................................ ................................ ....... 35 a.4 s ingle power (3.3v) application ................................ ................................ ................................ ................. 35 a.5 d ual power (5v and 3.3v) application with 3.3v phy ................................ ................................ ............. 36 appendix b: application note 2 ................................ ................................ ................................ .............. 37 b.1 a dvance a pplication for u sing c rystal ................................ ................................ ................................ ... 37 errata of ax88190 v1 ................................ ................................ ................................ ................................ ..... 38
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 4 figures f ig - 1 ax88190 b lock d iagram ................................ ................................ ................................ .............................. 5 f ig - 2 ax88190 p in c onnection d iagram ................................ ................................ ................................ ............... 6 tables t ab - 1 pcmcia bus interface signals group ................................ ................................ ................................ ........ 7 t ab - 2 eeprom bus interface signals group ................................ ................................ ................................ ........ 8 t ab - 3 mii interface signals group ................................ ................................ ................................ ........................ 8 t ab - 4 m odem interface signals group ................................ ................................ ................................ .................. 9 t ab - 5 sram i nterface pins group ................................ ................................ ................................ ......................... 9 t ab - 6 m iscellaneous pins group ................................ ................................ ................................ .......................... 10 t ab - 7 p ower on c onfiguration s etup t able ................................ ................................ ................................ ...... 10 t ab - 8 eeprom m emory m apping ................................ ................................ ................................ ........................ 11 t ab - 9 a ttribute m emory m apping ................................ ................................ ................................ ...................... 11 t ab - 10 i/o a ddress m apping ................................ ................................ ................................ ................................ 12 t ab - 11 l ocal m emory m apping ................................ ................................ ................................ ........................... 12 t ab - 12 pcmcia f unction c onfiguration r egister m apping of lan ................................ ............................... 13 t ab - 13 pcmcia f unction c onfiguration r egister m apping of modem ................................ ........................ 16 t ab - 14 p age 0 of mac c ore r egisters m apping ................................ ................................ ................................ . 18 t ab - 15 p age 1 of mac c ore r egisters m apping ................................ ................................ ................................ . 19
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 5 1.0 introduction 1.1 general description: the ax88190 provides industrial standard ne2000 registers level compatable instruction set. various drivers are easy acquired, maintenance and usage with no pain and tears the ax88190 fast ethernet controller is a high performance pc mc i a bus ethernet controller. the ax88190 contains a 16 bit pc mc i a interf ace s to host cpu and compliant with pc card standard ? february 1995 . the ax88190 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the ax88190 supports 10mbps/100mbps media-independent interface (mii) to simplify the design. the ax88190 is built in interface to connect fax/modem chipset with parallel bus interface. ax88190a use 128-pin lqfp low profile package, 2 5mhz o peration frequency , dual 5v and 3.3 v cmos process with 5v i/o tolerance or pure 3.3v operation. 1.2 ax88190 block diagram: fig - 1 ax88190 block diagram mac core sram arbiter remote dma fifos ne2000 registers pcmcia interface sta seeprom loader i/f sd[15:0] sa[9:0] ctl bus mii i/f smdc smdio memd[15:0] mema[15:1] eecs eeck eedi eedo modem i/f
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 6 1.3 ax88190 pin connection diagram the ax88190 is housed in the 128-pin plastic light quad flat pack fig - 2 ax88190 pin connection diagram shows the ax88190 pin assignment. fig - 2 ax88190 pin connection diagram mpwdn 123 118 122 78 70 54 41 32 24 12 8 memd[0] lvdd 117 75 57 42 26 31 21 sa[1] mreset# vss mint 107 105 66 65 63 60 25 16 13 3 7 vss mrdy lclk/xtalin hvdd 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 lvdd 68 58 56 55 45 23 vss 53 116 113 59 36 34 1 vss 124 108 hvdd ppwdn maudio mdcs# 28 22 9 hvdd lvdd vss 126 119 110 121 79 74 80 72 46 29 52 10 mrin# 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 vss iois16# vss 40 37 50 18 14 ax88190 pcmcia 10/100base mac controller 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 tx_en tx_clk vss mdc mdio rxd[3] rxd[2] rxd[1] rxd[0] lvdd rx_clk crs col rx_dv memd[1] memd[2] memd[3] memd[4] memd[5] memd[6] memd[7] memd[8] memd[9] memd[10] memd[11] memd[12] memd[13] memd[14] memd[15] mema[1] rx_er mema[2] mema[3] mema[4] mema[5] mema[6] mema[7] mema[8] mema[9] mema[10] mema[11] mema[12] mema[13] mema[14] mema[15] memrd# memwr# sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] ireq# we# iord# iowr# oe# sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] wait# reset inpack# ce2# ce1# txd[0] txd[1] txd[2] txd[3] xtalout eedi eedo eeck eecs stschg# spkr# reg# lvdd lvdd vss vss vss vss hvdd vss 64 clko25m
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 7 2.0 signal description the following terms d escribe the ax88190 pin-out: all pin names with the ? # ? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output pd pull down i/o input/output p power pin od open drain 2.1 pcmcia bus i nterface s ignals g roup signal type pin no. description sa [9:0] i 10 ? 1 system address : signals sa[9:0] are address bus input lines which enable direct address of up to 64k memory and i/o spaces on card. sd[15:0] i/o 20 ? 23, 25 ? 38, 30 ? 33, 35 ? 38 system data bus : signals sd[15:0] constitute the bi-directional data bus. ireq# o 12 interrupt request : ireq# is asserted to indicate the host system that the pc card device requires host software service. wait# o 125 wait : this signal is set low to insert wait states during remote dma transfer. reg# i 123 attribute memory and i/o space select : when the reg# signal is asserted, access is limited to attribute memory and to the i/o space. iord# i 15 i/o read : the host asserts iord# to read data from ax88190 i/o space. iowr# i 14 i/o write : the host asserts iowr# to write data into ax88190 i/o space. oe# i 16 output enable : the oe# line is used to gate memory read data from memory on pc card we# i 13 write enable : the we# signal is used for strobing memory write data into the memory on pc card. iois16# o 120 i/o is 16 bit port : the iois16# is asserted when the address at the socket corresponds to an i/o address to which the card responds, and the i/o port addressed is capable of 16-bit access. inpack# o 124 input port acknowledge : the signal is asserted when the ax88190 is selected and can respond to and i/o read cycle at the address on the address bus. ce1 # -ce2 # i 18, 17 card enable : the ce1# enables even numbered address bytes and ce2# enables odd numbered address bytes bvd1_stschg# o 121 battery voltage detect 1 / status change bvd2_spkr# o 122 battery voltage detect 2 / audio speaker out tab - 1 pcmcia b us interface signals group
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 8 2.2 eeprom s ignals g roup signal type pin no. description eecs o 106 eeprom chip select : eeprom chip select signal. eeck o 107 eeprom clock : signal connected to eeprom clock pin. eedi o 108 eeprom data in : signal connected to eeprom data input pin. eedo i /pu 109 eeprom data out : signal connected to eeprom data output pin. tab - 2 eeprom bus interface signals group 2.3 mii interface signals group signal type pin no. description rxd[3:0] i 90 ? 87 receive data : rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i 85 carrier sense : asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. rx_dv i 83 receive data valid : rx_dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er i 82 receive error : rx_er ,is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_clk i 86 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd[3:0] and rx_er signals from the phy to the mii port of the repeater. col i 84 collision : this signal is driven by phy when collision is detected. tx_en o 95 transmit enable : tx_en is transition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o 99 ? 96 transmit data : txd[3:0] is transition synchronously with respect to the rising edge of tx_clk. for each tx_clk period in which tx_en is asserted, txd[3:0] are accepted for transmission by the phy. tx_clk i 94 transmit clock : tx_clk is a continuous clock from phy. it provides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o 92 station management data clock : the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. mdc is a 2.5mhz frequency clock output. mdio i/o/pu 91 station management data input / output : serial data input/output transfers from/to the phys . the transfer protocol conforms to the ieee 802.3u mii specification. tab - 3 mii interface signals group
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 9 2.4 modem interface pins group signal name type pin no. description mrdy i/pu 118 modem ready : mrdy low indicates that modem is initializing the modem after reset signal asserted or the modem is at sleep/stop mode. mreset # o 117 modem reset : this signal asserts low to reset the modem chipset. mdcs # o 111 modem chip select : this signal connected to modem chip select pin. mpwdn o 116 modem power down : rockwell modem chipset, this signal asserts low to let modem chipset into power down mode. at&t modem chipset, this signal asserts high to let modem chipset into power down mode. mint i/pd 112 modem interrup t : this signal driven by modem chipset to active interrup t . mrin# i/pu 115 ring input : this signal is driven by daa ? s ring detect circuit. when a tel e phone ringing signal is being received. maudio i/pd 113 modem audio : this signal is passed to pcmcia interface via spkr. tab - 4 modem interface signals group 2.5 sram interface pins group signal type pin no. description mema [15:1] o 43, 45 ? 48, 50 ? 53 ? 55 ? 58, 60 ? 61 sram address : memd[15:0] i/o /pu 62 ? 63, 65 ? 68, 70 ? 74, 76 ? 80 sram data : memrd # o 42 sram read memwr # o 41 sram write tab - 5 sram interface pins group
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 10 2.6 miscellaneous pins group signal type pin no. description lclk/xtalin i 103 cmos local clock : a 25mhz clock, +/- 100 ppm, 40%-60% duty cycle. crystal oscillator input : a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. xtalout o 104 crystal oscillator output : a 25mhz crystal, +/- 25 ppm can be connected across xtalin and xtalout. if a single-ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. clko25m o 101 clock output 25mhz : this clock is source from lclk/xtalin. ppwdn o 114 phy power down : this pin connects to phy chip power down mode control input. reset i /pd 127 reset reset is active high then place ax88190 into reset mode immediately. during falling edge the ax88190 loads the eeprom data. lvdd p 44, 54, 100, 110, 126, 128 power supply : +3.3v dc. hvdd p 19, 29, 64, 75 power supply : +5v dc. note : for pure 3.3v single power solution, all the hvdd pin can connect to +3.3v. care should be taken that hvdd input power must be greater or equal ( > = ) than lvdd. vss p 11, 24, 34, 39, 40, 49, 59, 69, 81, 93, 102, 105, 119 power supply : +0v dc or ground power. tab - 6 miscel laneous pins group 2.7 power on configuration setup signals cross reference table signal name share with description eeprom size mem d [6] eeprom size = 0 : test mode. eeprom size = 1 : normal operation. (default) mpd_set memd[5] mpd_set = 0 : mpwdn pin active high. mpd_set = 1 : mpwdn pin active low. ppd_set memd[4] ppd_set = 0 : ppwdn pin active high. ppd_set = 1 : ppwdn pin active low. test memd[3] test = 0 : test mode. test = 1 : normal operation. (default) all of the above signals are pull-up for default values. tab - 7 power on configuration setup table
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 11 3.0 memory and i/o mapping there are four memory or i/o mapping used in ax88190. 1. eeprom memory mapping 2. attribute memory mapping 3. i/o mapping 4. local memory mapping 3.1 eeprom memory mapping eeprom offset high byte low byte 00h reserved word count 01h cfh cfl 02h node-id1 node id 0 03h node id 3 node id 2 04h node id 5 node id 4 05h checksum reserved 06h ? 10h reserved reserved 10h ? ffh cis cis tab - 8 eeprom memory mapping 3.2 attribute memory mapping attribute memory offset contents 00 00 h 03bfh cis 03c0h lcor 03c2h lccsr 03c4h - 03c6h - 03cah liobase0 03cch liobase1 03ceh 03dfh reserved 03e0h mcor 03e2h mccsr 03e4h - 03e6h - 03eah miobase0 03ech miobase1 03eeh 03ffh reserved tab - 9 attribute memory mapping
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 12 3.3 i/o mapping system i/o offset function 00 00 h 001fh mac core register tab - 10 i/o address mapping 3.4 sram memory mapping offset function 00 00 h 03bfh cis *1 03c0h l cor *1 03c2h l ccsr *1 03c4h - 03c6h - 03cah l iobase0 *1 03cch l iobase1 *1 03ceh 03dfh reserved 03e0h mcor *1 03e2h mccsr *1 03e4h - 03e6h - 03eah miobase0 *1 03ech miobase1 *1 03eeh 03ffh reserved 0400h node id 0 0401h node id 1 0402h node id 2 0403h node id 3 0404h node id 4 0405h node id 5 0406h 07ffh reserved 0800h ffffh 62 k x 8 sram buffer tab - 11 local memory mapping
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 13 4.0 registers operation the re are four register sets in ax88190 : 1. the pcmcia function configuration registers of lan . 2. the pcmcia function configuration registers of modem . 3. t he mac core register . 4. t he special register s . 4.1 pcmcia function configuration register set of lan register name offset lcor configuration option register 3c 0h l csr configuration and status register 3c2h l iobase0 i/o based register 0 3cah l iobase1 i/o based register 1 3cch tab - 12 pcmcia function configuration register mapping of lan
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 14 4.1.1 configuration option register of lan (lcor) offset 3c0h (read/write) field r/w/c description 7 r/w software reset assert this bit will reset the lan function of ax88190 . return a 0 to this bit will leave the lan function of ax88190 in a post-reset state as same as that following a hardware reset. the value of this bit is 0 at power-on. 6 r/w level irq this bit should be set to 1, the ax88190 always generates level mode interrupt. 5:0 r/w function configuration index these six bits are used to indicate entry of the card configuration table locate in the cis. the default value is 0 . on multifunction pc card, bit 5, bit 4 : modem i/o base registers bit 5 bit 4 modem i/o base 0 0 decided by miobase registers ( see section 4.2.3 ) 0 1 2f8h 1 0 3e8h 1 1 2e8h bit 3 : enable power down mode if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1, the lan will go into power down mode. at power down mode ax88190 will disable mac transmitting and receiving operation. but the host interface will not be affected. bit 2 : enable ireq# routing if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1, the lan will generate interrupt request via ireq# signal. if this bit is set to 0, the lan will not generate interrupt request via ireq# line. bit 1 : enable base and limit registers if bit 0 of lcor is set to 0, this bit is ignored. if bit 0 of lcor is set to 1 and this bit is set to 1,only i/o addresses that are qualified by the base and limit registers are passed to lan function. if this bit is set to 0,all i/o addresses are passed to lan function. bit 0 : enable function if this bit is set to 0, the lan function is disabled. if this bit is set to 1, the lan function is enabled.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 15 4.1.2 configuration and status register of lan (l cs r) offset 3c2h (read/write) field r/w/c description 7:3 - reserved 2 r/w ppwrdwn : phy power down setting while this bit set to 1, ppwdn pin (pin 114) will be active to force phy chip into power down mode. as for ppwdn is active high or active low. please refer section 2.7 power on configuration setup signal cross reference table. 1 r intr : interrupt request the lan function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. 0 r intrack : interrupt acknowledge this bit will be 0. the intr will reflect the status of interrupt requesting. 4.1.3 i/o base register 0/1 of lan (liobase0/1) offset 3cah/3cch (read/write) the i/o base registers (liobase0 and liobase1) determine the base address of the i/o range used to access the lan specific registers (mac core registers). i/o base register 0 field r/w/c description 7:0 r/w base i/o address bit 7 ? 0. i/o base register 1 field r/w/c description 7:0 r/w base i/o address bit 15 ? 8.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 16 4.2 pcmcia function configuration register set of modem register name offset mcor configuration option register 3e 0h m csr configuration and status register 3e2h m iobase0 i/o based register 0 3eah m iobase1 i/o based register 1 3ech tab - 13 pcmcia function configuration register mapping of modem 4.2.1 configuration option register of modem (mcor) offset 3e0h (read/write) field r/w/c description 7 r/w software reset assert this bit will reset the modem function of ax88190 . return a 0 to this bit will leave the modem function of ax88190 in a post-reset state as same as that following a hardware reset. the value of this bit is 0 at power-on. 6 r/w level irq this bit should be set to 1, the ax88190 always generates level mode interrupt. 5:0 r/w function configuration index these six bits are used to indicate entry of the card configuration table locate in the cis. the default value is 0 . on multifunction pc card, bit 5, bit4 : reserved bit 3 : ireq# route to stschg# if bit 0 of mcor is set to 0, this bit is ignored. if both bit 0 and bit 2 of mcor are set to 1 and this bit is set to 1, the modem will route interrupt request to stschg# signal. if this bit is set to 0, the modem will generate interrupt request via ireq# line. bit 2 : enable ireq# routing if bit 0 of mcor is set to 0, this bit is ignored. if bit 0 of mcor is set to 1 and this bit is set to 1, the modem will generate interrupt request via ireq# signal. if this bit is set to 0, the modem will not generate interrupt request via ireq# line. bit 1 : enable base and limit registers if bit 0 of mcor is set to 0, this bit is ignored. if bit 0 of mcor is set to 1 and this bit is set to 1,only i/o addresses that are qualified by the base and limit registers are passed to modem function. if this bit is set to 0,all i/o addresses are passed to lan function. bit 0 : enable function if this bit is set to 0, the modem function is disabled. if this bit is set to 1, the modem function is enabled.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 17 4.2.2 configuration and status register of modem (m cs r) offset 3e2h (read/write) field r/w/c description 7:3 - reserved 2 r/w mpwrdwn : modem power down setting while this bit set to 1, mpwdn pin (pin 116) will be active to force modem chip into power down mode. as for mpwdn is active high or active low. please refer section 2.7 power on configuration setup signal cross reference table. 1 r intr : interrupt request the lan function will set this bit to 1 when it need interrupt service and set it to 0 when it is not request interrupt service. 0 r intrack : interrupt acknowledge this bit will be 0. the intr will reflect the status of interrupt requesting. 4.2.3 i/o base register 0/1 of modem (miobase0/1) offset 3eah/3ech (read/write) the i/o base registers (miobase0 and miobase1) determine the base address of the i/o range used to access the modem specific registers. i/o base register 0 field r/w/c description 7:0 r/w base i/o address bit 7 ? 0. i/o base register 1 field r/w/c description 7:0 r/w base i/o address bit 15 ? 8.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 18 4.3 registers operation all registers of mac core are 8-bit wide and mapped into pages which are selected by ps in the command register. page 0 (ps 1 =0 ,ps0=0 ) offset read write 00h command register ( cr ) command register ( cr ) 01h page start register ( pstart ) page start register ( pstart ) 02h page stop register ( pstop ) page stop register ( pstop ) 03h boundary pointer ( bnry ) boundary pointer ( bnry ) 04h transmit status register ( tsr ) transmit page start address ( tpsr ) 05h number of collisions register ( ncr ) transmit byte count register 0 ( tbcr0 ) 06h current page register ( cpr ) transmit byte count register 1 ( tbcr1 ) 07h interrupt status register ( isr ) interrupt status register ( isr ) 08h current remote dma address 0 ( crda0 ) remote start address register 0 ( rsar0 ) 09h current remote dma address 1 ( crda1 ) remote start address register 1 ( rsar1 ) 0ah reserved remote byte count 0 ( rbcr0 ) 0bh reserved remote byte count 1 ( rbcr1 0 0ch receive status register ( rsr ) receive configuration register ( rcr ) 0dh frame alignment errors ( cntr0 ) transmit configuration register ( tcr ) 0eh crc errors ( cntr1 ) data configuration register ( dcr ) 0fh missed packet errors ( cntr2 ) interrupt mask register ( imr ) 10h 11h data port data port 12h ifgs1 ifgs1 13h ifgs2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h to 1eh reserved reserved 1fh reset reserved tab - 14 page 0 of mac core registers mapping
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 19 page 1 ( ps1=0, ps 0 =1) offset read write 00h command register ( cr ) command register ( cr ) 01h physical address register 0 ( para0 ) physical address register 0 ( par0 ) 02h physical address register 1 ( para1 ) physical address register 1 ( par1 ) 03h physical address register 2 ( para2 ) physical address register 2 ( par2 ) 04h physical address register 3 ( para3 ) physical address register 3 ( par3 ) 05h physical address register 4 ( para4 ) physical address register 4 ( par4 ) 06h physical address register 5 ( para5 ) physical address register 5 ( par5 ) 07h current page register ( cpr ) current page register ( cpr ) 08h multicast address register 0 ( mar0 ) multicast address register 0 ( mar0 ) 09h multicast address register 1 ( mar1 ) multicast address register 1 ( mar1 ) 0ah multicast address register 2 ( mar2 ) multicast address register 2 ( mar2 ) 0bh multicast address register 3 ( mar3 ) multicast address register 3 ( mar3 ) 0ch multicast address register 4 ( mar4 ) multicast address register 4 ( mar4 ) 0dh multicast address register 5 ( mar5 ) multicast address register 5 ( mar5 ) 0eh multicast address register 6 ( mar6 ) multicast address register 6 ( mar6 ) 0fh multicast address register 7 ( mar7 ) multicast address register 7 ( mar7 ) 10h 11h data port data port 12h inter-frame gap segment 1 ifgs1 inter-frame gap segment 1 ifgs1 13h inter-frame gap segment 2 ifgs2 inter-frame gap segment 2 ifgs2 14h mii/eeprom access mii/eeprom access 15h - test register 16h inter-frame gap ( ifg ) inter-frame gap ( ifg ) 17h to 1eh reserved reserved 1fh reset reserved tab - 15 page 1 of mac core registers mapping
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 20 4.3.1 command register (cr) offset 00h (read/write) field name description 7 :6 ps 1,ps0 ps 1,ps0 : page select the two bit selects which register page is to be accessed. ps1 ps0 0 0 page 0 0 1 page 1 5:3 rd2,rd1 ,rd0 rd2,rd1,rd0 : remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by ax88190 when a remote dma has been completed. the remote byte count should be cleared when a remote dma has been aborted. the remote start address are not restored to the starting address if the remote dma is aborted. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma 2 txp txp : transmit packet this bit could be set to initiate transmission of a packet 1 start start : this bit is used to active ax88190 operation. 0 stop stop : stop ax88190 this bit is used to stop the ax88190 operation. 4.3.2 interrupt status register (isr) offset 07h (read/write) field name description 7 rst reset status : set when ax88190 enters reset state and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed 5 cnt counter overflow set when msb of one or more of the tally counters has been set. 4 ovw overwrite : set when receive buffer ring storage resources have been exhausted. 3 txe transmit error set when packet transmitted with one or more of the following errors n excessive collisions n fifo under - run 2 rxe receive error indicates that a packet was received with one or more of the following errors crc error frame alignment error fifo overrun missed packet 1 ptx packet transmitted indicates packet transmitted with no error 0 prx packet received indicates packet received with no error.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 21 4.3.3 interrupt mask register (imr) offset 0fh (write) field name description 7 - reserved 6 rdce dma complete interrupt enable. default ? low ? disabled. 5 cnte counter overflow interrupt enable. default ? low ? disabled. 4 ovwe overwrite interrupt enable. default ? low ? disabled. 3 txee transmit error interrupt enable. default ? low ? disabled. 2 rxee receive error interrupt enable. default ? low ? disabled. 1 ptxe packet transmitted interrupt enable. default ? low ? disabled. 0 prxe packet received interrupt enable. default ? low ? disabled. 4.3.4 data configuration register ( dcr ) offset 0eh (write) field name description 7 rdcr remote dma always completed 6:2 - reserved 1 bos byte order select 0: ms byte placed on ad15:ad8 and ls byte on ad7-ad0 (80x86). 1: ms byte placed on ad7::ad0 and ls byte on ad15:ad0(68k) 0 wts word transfer select 0 : selects byte-wide dma transfers. 1 : selects word-wide dma transfers. 4.3.5 transmit configuration register (tcr) offset 0dh (write) field name description 7 fdu full duplex : this bit indicates the current media mode is full duplex or not. 0 : half duplex 1 : full duplex 6 pd pad disable 0 : pad will be added when packet length less than 60. 1 : pad will not be added when packet length less tha n 60. 5 rlo retry of late collision 0 : don ? t retransmit packet when late collision happens. 1 : retransmit packet when late collision happens. 4:3 - reserved 2:1 lb1,lb0 encoded loop-back control these encoded configuration bits set the type of loop-back that is to be performed. lb1 lb0 mode 0 0 0 normal operation mode 1 0 1 internal nic loop-back mode 2 1 0 phycevisor loop-back 0 crc inhibit crc 0 : crc appended by transmitter. 1 : crc inhibited by transmitter.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 22 4.3.6 transmit status register (tsr) offset 04h (read) field name description 7 owc out of window collision 6:4 - reserved 3 abt transmit aborted indicates the ax88190 aborted transmission because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 4.3.7 receive configuration (rcr) offset 0ch (write) field name description 7 - reserved 6 intt interrupt tri g ger mode must be setting to ? 1 ? . 5 mon monitor mode 0 : normal operation 1 : monitor mode, the input packet will be checked on node address and crc but not buffered into memory. 4 pro pro : promiscuous mode enable the receiver to accept all packets with a physical address. 3 am am : accept multicast enable the receiver to accept packets with a multicast address. that multicast address must pass the hashing array. 2 ab ab : accept broadcast enable the receiver to accept broadcast packet. 1 ar ar : accept runt enable the receiver to accept runt packet. 0 sep sep : save error packet enable the receiver to accept and save packets with error. 4.3.8 receive status register (rsr) offset 0ch (read) field name description 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 fo fifo overrun 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact 4.3.9 inter-frame gap (ifg) offset 16h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap . default value 15h.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 23 4.3.10 inter-frame gap segment 1 ( ifgs1 ) offset 12h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 1 . default value 0ch. 4.3.11 inter-frame gap segment 2 ( ifgs2 ) offset 13h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 2 . default value 11h. 4.3.12 mii/eeprom management register ( memr ) offset 14h (read/write) field name description 7 eeclk eeclk : eeprom clock 6 eeo eeo : (read only) eeprom data out value. that reflects pin-109 eedo value. 5 eei eei eeprom data in . that output to pin-108 eedi as eeprom data input value. 4 eecs eecs eeprom chip select 3 mdo mdo mii data out 2 mdi mdi : (read only) mii data in . that reflects pin-91 mdio value. 1 m dir mii sta mdio signal direction mii read control bit, assert this bit let mdio signal as the input signal. deassert this bit let mdio as output signal. 0 mdc mdc mii clock 4.3.13 test register (tr) offset 15h (write) field name description 7:5 - reserved 4 tf16t test for collision 3 tpe test pin enable 2:0 ifg select test pins output
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 24 5.0 pcmcia device access functions the ax88190 , as a pcmcia i/o device , needs support both attribute memory access function and i/o access function. the access methods are described as the following sections. 5.1 attribute memory access function functions. attribute memory read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high-z high-z byte access (8 bits) l l h h l l l h l l h h high-z high-z even-byte not valid word access (16 bits) l l l x l h not valid even-byte odd byte only access l l h x l h not valid high-z attribute memory write function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even-byte x word access (16 bits) l l l x h l x even-byte odd byte only access l l h x h l x x 5.2 i/o access function functions. i/o read function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x high-z high-z byte access (8 bits) l l h h l l l h l l h h high-z high-z even-byte odd-byte word access (16 bits) l l l l l h odd-byte even-byte i/o inhibit h x x x l h high-z high-z odd byte only access l l h x l h odd-byte high-z i/o write function function mode reg# ce2# ce1# sa0 iord# iowr# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even-byte odd-byte word access (16 bits) l l l l h l odd-byte even-byte i/o inhibit h x x x h l x x odd byte only access l l h x h l odd-byte x
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 25 6.0 electrical specification and timings 6.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts -55 +150 c supply voltage hvdd -0.3 +6 v supply voltage lvdd -0.3 +4.6 v input voltage hvin lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v output voltage hvout lvin -0.3 -0.3 hvdd+0.5 lvdd+0.5 v v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +75 c supply voltage hvdd lvdd +4.75v +2.70 +3.00 +5.00v +3.00 +3.30 +5.25v +3.30 +3.60 v v v note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 6.3 dc characteristics (vdd=5.0v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 2 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 1.9 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua description sym min tpy max units power consumption (dual power) dpt5v dpt3v 22 40 ma ma power consumption (single power 3.3v) spt3v 48 ma
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 26 6.4 a.c. timing characteristics 6.4.1 xtal / clock lclk/xtalin tr tf tlow clk25m tod symbol description min typ. max units t cyc cycle time 40 ns t high clk high time 16 20 24 ns t low clk low time 16 20 24 ns t r/ t f clk slew rate 1 - 4 ns tod lclk/xtalin to clk25m out delay 10 6.4.2 reset timing lclk reset symbol description min typ. max units trst reset pulse width 100 - - lclk tcyc thigh
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 27 6.4.3 attribute memory read timing tcr ta(a) th(a) a[9:0], reg# ta(ce) t v(a) tsu(ce) ce# tsu(a) ta(oe) th(ce) oe# tv(wt-oe) tw(wt) tdis(ce) wait# ten(oe) tv(wt) tdis(oe) d[15:0] data valid symbol description min typ. max units t cr read cycle time 300 - - ns t a(a) address access time - - 120 ns t a(ce) card enable access time - - 100 ns t a(oe) output enable access time - - 100 ns t dis(oe) output disable time from oe# 0.5 - - ns t en(oe) output enable time from oe# - - 100 ns t v(a) data valid from address change 0 - - ns t su(a) address setup time 30 - - ns t h(a) address hold time 20 - - ns t su(ce) card enable setup time 0 - - ns t h(ce) card enable hold time 20 - - ns t v(wt-oe) wait# valid from oe# - - 10 ns t w(wt) wait# pulse width - - 200 ns t v(wt) data setup for wait# released 100 - - ns
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 28 6.4.4 attribute memory write timing tcw a[9:0], reg# tsu(ce-weh) ce# tsu(ce) tsu(a-weh) th(ce) oe# tsu(a) tw(we) trec( we) we# tv(wt-we) tv(wt) tw(wt) th(oe-we) wait# tsu(oe-we) tsu(d-weh) th(d) d[15:0](din) data input establish tdis(we) ten(oe) tdis(oe) ten(we) d[15:0](dout) symbol description min typ. max units t cw write cycle time 250 - - ns t w(we) write pulse width 150 - - ns t su(a) address setup time 30 - - ns t su(a-weh) address setup time for we# 180 - - ns t su(ce-weh) card enable setup time for we# 180 - - ns t su(d-weh) data setup time for we# 80 - - ns t h(d) data hold time 30 - - ns t rec(we) write recover time 30 - - ns t dis(we) output disable time from we# - - 5 ns t dis(oe) output disable time from oe# - - 5 ns t en(we) output enable time from we# 5 - - ns t en(oe) output enable time from oe# 5 - - ns t su(oe-we) output enable setup time from oe# 10 - - ns t h(oe-we) output enable hold time from oe# 10 - - ns t su(ce) card enable setup time 0 - - ns t h(ce) card enable hold time 20 - - ns t v(wt-we) wait# valid from we# - - 15 ns t w(wt) wait# pulse width - - 200 ns t v(wt) we# high from wait# released 0 - - ns
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 29 6.4.5 i/o read timing a[9:0] tha tsureg threg reg# tsuce th ce ce# tw iord# tsua td rinpack inpack# tdfinpack tdriois16 iois16# tdfiois16 td tdr(wt) wait# tdfwt tw(wt) th d[15:0] data valid symbol description min typ. max units t d data delay after iord# - - 50 ns t h data hold following iord# 0.5 - - ns t w iord# width time 165 - - ns t sua address setup before iord# 70 - - ns t ha address hold before iord# 20 - - ns t suce ce# setup before iord# 5 - - ns t hce ce# hold before iord# 20 - - ns t sureg reg# setup before iord# 5 - - ns t hreg reg# hold before iord# 0 - - ns t dfinpack inpack# delay falling from iord# 0 - 10 ns t drinpack inpack# delay rising from iord# - - 10 ns t dfiois16 iois16# delay falling from address* - - 10 ns t driois16 iois16# delay rising from address* - - 0 ns t dfwt wait# delay falling from iord# - - 5 ns t dr(wt) data delay from wait# rising - - 0 us t w(wt) wait# width time - - 100 ns * note : the address includes reg# and ce1# signal
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 30 6.4.6 i/o write timing a[9:0] tha tsureg threg reg# tsuce th ce ce# tw iowr# tsua tdriois16 iois16# tdfiois16 tdriowr wait# tdfwt tw(wt) th tsu d[15:0] data symbol description min typ. max units t su data setup before iowr# 60 - - ns t h data hold following iowr# 30 - - ns t w iowr# width time 165 - - ns t sua address setup before iowr# 70 - - ns t ha address hold before iowr# 20 - - ns t suce ce# setup before iowr# 5 - - ns t hce ce# hold before iowr# 20 - - ns t sureg reg# setup before iowr# 5 - - ns t hreg reg# hold before iowr# 0 - - ns t dfiois16 iois16# delay falling from address* - - 10 ns t driois16 iois16# delay rising from address* - - 0 ns t dfwt wait# delay falling from iowr# - - ** ns t w(wt) wait# width time - - ** ns t driowr iowr# high from wait# high 0 - - us *note : the address includes reg# and ce1# signal ** note : there is no wait state while i/o write operation
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 31 6.4.7 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 32 6.4.8 asynchronous memory i/f access timing memory write tsu(a) th(a) mema[15:1] tw(wr) /memwr td(wtor) tw(rddis) /memrd tsu(d) th(d) write data sd[15:0](dout) data valid symbol description min typ. max units t su(a) address setup time 36 - - ns t h(a) address hold time 0.3 - 1 ns t w(wr) write pulse width * - ns t w(rddis) read disable pulse width * - ns t d(wtor) write to read dealy 1 - 4.5 ns t su(d) data setup time 16 - - ns t h(d) data hold time 0.3 - 2 ns memory read tsu(a) th(a) mema[15:1] referance tw(rd) internal ? /memrd ? ( high level ) /memwr ( low level ) /memrd tsu(rd) th(rd) read data memd[15:1] valid data symbol description min typ. max units t su(a) address setup time 30 - - ns t h(a) address hold time 1.3 - 1 ns t w(rd) read pulse width * - ns t su(d) data setup time 3 - - ns t h(d) data hold time 0 - 2 ns * note : the pulse width can be seen as lclk/xtalin high time. see also 6.4.1 ? thigh ? parameter. note : all most any brand asynchronous sram access time under 20 ns can fit into the specification.
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 33 7.0 package information b e d hd e he pin 1 a2 a1 l l1 q a milimeter symbol min. nom max a1 0.1 a2 1.3 1.4 1.5 a 1.7 b 0.155 0.16 0.26 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.60 16.00 16.40 he 15.60 16.00 16.40 l 0.30 0.50 0.70 l1 1.00 q 0 10
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 34 appendix a: application note 1 a.1 using crystal ax88190 to phy clko25m xtalin xtalout 25mhz crystal 8pf 2mohm 8pf note : the capacitors (8pf) may be various depend on the specification of crystal. while designing, please refer to the suggest circuit provided by crystal supplier. a.2 using oscillator ax88190 to phy clko25m xtalin xtalout nc 3.3v power osc 25mhz
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 35 a.3 dual power (5v and 3.3v) application +5v +5v +3.3v (option for core logic) +5v hvdd +5v +3.3v lvdd +5v a.4 single power (3.3v) application +3.3v +3.3v +3.3v hvdd +3.3v +3.3v lvdd +3.3v ax88190 phy/txrx modem daa magnetic rj45 rj11 +5v pcmcia i/f eeprom sram ax88190 phy/txrx modem daa magnetic rj45 rj11 +3.3v pcmcia i/f eeprom sram
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 36 a.5 dual power (5v and 3.3v) application with 3.3v phy the 510 and 1k ohm resisters are just for voltage adjustment ax88190 phy rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio rxd[3:0] crs rx_dv rx_er rx_clk col tx_en txd[3:0] tx_clk mdc mdio 510 ohm 1k ohm
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 37 appendix b: application note 2 b.1 advance application for using crystal date: may 21, 1999 condition : in short cable, ax88190 +ah 101 phyceiver can ? t link to bcm 5308 switch. conclusion : 1. after measuring and verifying, we found it ? s relevant to clock source . 2. we ascertain the problem is caused by matching issues between crystal and capacitor . solution : change the value of capacitors beside crystal as below : note: the capacitors may be various depend on the specification of crystal. while designing , please refer to the circuit provided by crystal supplier . xin xout y1 25mhz c22 18p c23 18p r4 2m
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 38 errata of ax88190 v1 1. oe# synchronous problem result in pc hang solution : using hardware ckt to pre-sync oe# signal as below. 2. interrupt status can ? t always clean up solution : using software to do clean and check iteration until clean up. ex : iobase=300 ; clear tx/rx interrupt. mov dx,307h clrisr : mov al,3 ; clear tx/rx interrupt out dx,al ; output to clear isr in al,dx ; read isr test al,3 ; check isr cleared or not jz clrisrdone ; clear ok mov al,0 ; if not , clear again out dx,al jmp clrisr clrisrdone: ? ; clear successful 3. ce1# bus decoder problem solution : dis-connect ax88190 ce1# (pin 18) from pcmcia connector ce1# (pin 7). and connect ax88190 ce1# (pin 18) to logic ? 0 ? always enable this signal. from pcmcia connector pin 9 from ax88190 pin 101 to ax88190 pin 16 jumper for future use clk25m oe_# oe_m# u1b 74f74 d 12 clk 11 q 9 q 8 pr 10 cl 13 u1a 74f74 d 2 clk 3 q 5 q 6 pr 4 cl 1 u2a 74f86 1 2 3
asix electronics corporation 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http://www.asix.com.tw ax881 9 0 pcmcia fast ethernet mac controller asix 190lu1a.sch 1.0 pcmcia bus & ax88190 & memory asix electronics corporation b 1 3 tuesday, december 15, 1998 title size document number rev date: sheet of rxd3 rxd2 rxd1 rxd0 crs col rxdv rxer mdc mdio txen txd0 txd1 txd2 txd3 vdd gnd reset# pclk txclk rxclk |link (option for test) (ax88190 application used luc6612) |190lu1a1.sch memrd# ma11 ma12 gnd ma10 md15 ma9 md14 ma14 md13 gnd gnd sa0 lvdd memwr# md12 sd3 gnd sa1 reset vdd md11 sd4 sd11 sa2 lvdd ma15 gnd sd5 sd12 sa3 wait# ma13 md10 sd6 sd13 sa4 inpack# ma8 md9 sd7 sd14 sa5 reg# ma7 md8 sd15 sa6 spkr# ma6 ma1 ce2# sa7 stschg# ma5 ma2 oe# sa8 iois16# ma4 ma3 iord# sa9 gnd sa9 iowr# gnd sa8 ireq# we# iowr# memrd# ma11 we# iord# ma12 gnd ireq# oe_m# ma10 md7 vdd vdd ce2# ma9 md6 ma14 md5 vdd lvdd memwr# md4 sd15 eedo vdd md3 sd14 eedi ma15 gnd sa7 sd13 eesk ma13 md2 sa6 sd12 eecs ma8 md1 sa5 reset gnd gnd ma7 md0 sa4 wait# sd11 xout ma6 ma1 sa3 inpack# sd10 xin ma5 ma2 sa2 reg# sd9 gnd ma4 ma3 sa1 spkr# sd8 sa0 stschg# vdd lvdd sd0 sd8 sd7 sd1 sd9 sd6 sd2 sd10 sd5 iois16# gnd gnd gnd sd4 gnd sd3 sd2 gnd sd1 sd0 gnd gnd memwr# memrd# pclk eecs vdd ma15 eesk lvdd eedi ma14 eedo gnd ma13 ma12 ma11 gnd gnd md0 ma10 md1 ma9 md2 ma8 md3 ma7 md4 lvdd vdd xin xout ma6 md5 ma5 md6 ma4 md7 oe# oe_m# ma3 md8 gnd md9 ma2 gnd ma1 md10 md15 md11 md14 md12 vdd md13 vdd vdd lvdd gnd gnd lvdd gnd u1 pcmcia gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1# 7 a10 8 oe# 9 a11 10 a9 11 a8 12 a13 13 a14 14 we# 15 ireq# 16 vcc 17 vpp1 18 a16 19 a15 20 a12 21 a7 22 a6 23 a5 24 a4 25 a3 26 a2 27 a1 28 a0 29 d0 30 d1 31 d2 32 iois16# 33 gnd 34 gnd 35 cd1# 36 d11 37 d12 38 d13 39 d14 40 d15 41 ce2# 42 vs1# 43 iord# 44 iowr# 45 a17 46 a18 47 a19 48 a20 49 a21 50 vcc 51 vpp2 52 a22 53 a23 54 a24 55 a25 56 vs2# 57 reset 58 wait# 59 inpack# 60 reg# 61 spkr# 62 stschg# 63 d8 64 d9 65 d10 66 cd2# 67 gnd 68 u2 ax88190 sa[0] 1 sa[1] 2 sa[2] 3 sa[3] 4 sa[4] 5 sa[5] 6 sa[6] 7 sa[7] 8 sa[8] 9 sa[9] 10 vss 11 ireq# 12 we# 13 iowr# 14 iord# 15 oe# 16 ce2# 17 ce1# 18 hvdd 19 sd[15] 20 sd[14] 21 sd[13] 22 sd[12] 23 vss 24 sd[11] 25 sd[10] 26 sd[9] 27 sd[8] 28 hvdd 29 sd[7] 30 sd[6] 31 sd[5] 32 sd[4] 33 vss 34 sd[3] 35 sd[2] 36 sd[1] 37 sd[0] 38 vss 39 vss 40 memwr# 41 memrd# 42 lvdd 44 mema[14] 45 mema[13] 46 mema[12] 47 mema[11] 48 mema[10] 50 mema[9] 51 mema[8] 52 mema[7] 53 lvdd 54 mema[6] 55 mema[5] 56 mema[4] 57 mema[3] 58 vss 59 mema[2] 60 mema[1] 61 memd[15] 62 memd[14] 63 hvdd 64 mema[15] 43 vss 49 memd[13] 65 memd[12] 66 memd[11] 67 memd[11] 68 vss 69 memd[9] 70 memd[8] 71 memd[7] 72 memd[6] 73 memd[5] 74 hvdd 75 memd[4] 76 memd[3] 77 memd[2] 78 memd[1] 79 memd[0] 80 vss 81 rx_er 82 col 84 crs 85 rx_clk 86 rxd[0] 87 rxd[1] 88 rxd[2] 89 rxd[3] 90 mdio 91 mdc 92 vss 93 tx_clk 94 tx_en 95 txd[0] 96 txd[1] 97 txd[2] 98 txd[3] 99 lvdd 100 clko25m 101 vss 102 lclk/xtalin 103 xtalout 104 vss 105 eecs 106 lvdd 128 reset 127 lvdd 126 wait# 125 inpack# 124 reg# 123 spkr# 122 stschg# 121 iois16# 120 vss 119 mrdy 118 mreset# 117 mpwdn 116 mrin# 115 ppwdn 114 maudio 113 mint 112 mdcs# 111 lvdd 110 eedo 109 eedi 108 eeck 107 rx_dv 83 c1 4.7u/16v + c2 4.7u/16v + y1 25mhz r1 10k c3 0.01u c4 0.01u c5 0.01u c6 0.1u c7 0.1u c8 0.1u c9 0.1u c10 0.1u c11 0.1u c12 4.7u/16v + c13 0.01u c14 0.1u c15 0.1u c16 0.1u c17 0.1u c18 0.1u c19 0.1u c20 4.7u/16v + r2 20 c21 8p u4 is61c256ah #oe 22 a11 23 a9 24 a8 25 a13 26 #we 27 vcc 28 a14 1 a12 2 a7 3 a6 4 a5 5 a4 6 a3 7 a10 21 #ce 20 i/o7 19 i/o6 18 i/o5 17 i/o4 16 i/o3 15 gnd 14 i/o2 13 i/o1 12 i/o0 11 a0 10 a1 9 a2 8 u5 is61c256ah #oe 22 a11 23 a9 24 a8 25 a13 26 #we 27 vcc 28 a14 1 a12 2 a7 3 a6 4 a5 5 a4 6 a3 7 a10 21 #ce 20 i/o7 19 i/o6 18 i/o5 17 i/o4 16 i/o3 15 gnd 14 i/o2 13 i/o1 12 i/o0 11 a0 10 a1 9 a2 8 u6a 74f86 1 2 3 u7a 74f74 d 2 clk 3 q 5 q 6 pr 4 cl 1 u7b 74f74 d 12 clk 11 q 9 q 8 pr 10 cl 13 u8 93c56r cs 1 sk 2 di 3 do 4 gnd 5 nc 6 nc 7 vcc 8 r4 0 c22 8p r6 2m c23 8p u9 xc62fp tab 4 vin 2 vss 1 vout 3 c24 0.1u c25 0.1u c26 0.1u c27 0.1u c28 4.7u/16v + c29 0.01u
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 40 190lu1a1.sch 1.0 lucent luc6612 phy asix electronics co. b 2 3 tuesday, december 15, 1998 title size document number rev date: sheet of mdio mdc txen txd3 txd2 txd1 txd0 rxd3 rxd2 rxd1 rxd0 pclk rxer rxdv col crs vdd gnd reset# txclk rxclk by pass cap with digital power supply by pass cap with analog power supply phyad0 phyad1 phyad2 phyad3 phyad4 set phy address to 10000 to pcmj15 connect vdda gnd gnd rdp gnd rdn lled vdda aled vdd gnd pad4 vdd gnd tdp fled tdn sled gnd fled sled vdda vdd gnd aled gnd vdda lled gnd gnd gnd vdd pad4 gnd gnd vddpll fled fdled sled spled gnd gnd gnd aled acled lled liled vdd gnd gnd vdd vdd gnd vdd vdda tdp tdn gnd rdp rdn spled vdd vddpll liled gnd acled fdled chassis u10 luc6612 vccbg 1 iset_100 2 gndbg 3 led_link/phad0 4 led_act/phad1 5 vccioa 6 gndioa 7 td+ 8 td- 9 gndt 10 vcct 11 clkref 12 gndbt 13 vccbt 14 test0 15 test1 16 phad4 17 pcsen# 18 test2 19 vccpll 20 lsclk1 21 lsclk2 22 gndpll 23 iset_10 24 mdio 25 mdc 26 reset# 27 rx_en 28 tx_er/txd4 29 tx_en 30 txd3 31 txd2 32 txd1 33 txd0 34 vccdiga 35 gnddiga 36 rxd3 37 rxd2 38 rxd1 39 rxd0 40 gndioc 41 crs 42 col 43 rx_clk 44 rx_dv 45 rx_er/rxd4 46 tx_clk 47 gnddigb 48 vccdigb 49 mode0 50 mode1 51 mode2 52 gndiob 53 vcciob 54 led_fdx/phad3 55 led_spd/phad2 56 bgref1 57 bgref0 58 gndrec 59 vccrec 60 vcceqap 61 rd- 62 rd+ 63 gndeqap 64 l1 fb r7 24.9k r8 22.1k r10 4.7k r11 24.9k r12 24.9k u11 14st9012p ct 1 td+ 2 td- 3 rd+ 5 rd- 6 ct 7 ct 8 rx- 9 rx+ 10 tx- 12 tx+ 13 ct 14 j1 pcmj15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r13 49.9 r14 49.9 r15 49.9 r16 49.9 c31 0.01u r17 220 r18 220 r19 75 r20 75 r21 75 r22 75 c32 8p r23 33 r24 33 c33 8p r25 10k r26 10k r27 10k r28 10k r29 10k r30 510 r31 510 r32 510 r33 510 l2 fb c34 0.1u c35 0.01u c36 0.01u c37 0.01u c38 4.7u/16v + c39 0.01u c40 0.1u c41 0.1u c42 0.1u c43 0.1u c44 0.1u c45 4.7u/16v + c46 0.1u c47 0.1u c48 0.1u c49 0.1u c50 0.1u c51 0.01u c52 0.1u c53 0.01u/2kv c30 1000p
ax88190 pcmcia fast ethernet mac controller asix electronics corporation 41 190led.sch 1.0 rj45 & led asix electronics corporation a 3 3 tuesday, december 15, 1998 title size document number rev date: sheet of liled spled acled fdled chassis j2 rj45n 1 2 3 6 4 5 7 8 j3 con12 1 2 3 4 5 6 7 8 9 10 11 12 d1 led d2 led d3 led d4 led c54 0.01

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